Optionally an IRQ can be enabled to avoid busy waiting. Wait until the hardware-ready bit in GMBUS2 is set.The simplest way to use the bus is to program the bus cycle selects bits so that no index or STOP is generated and the bus just enters a wait state after the packet is transferred. Write the destination address, the byte count and the software-ready bit to the GMBUS1 register.Write the first 4 bytes of data to the GMBUS3 register.In order to send a packet to the bus the following steps suffice:

100 kHz is a conservative default choice. Intel graphics chips provide a relative straightforward way to interact with the I☬ bus.īefore using the I☬ bus a connector has to be selected in the GMBUS0 register.

EDID is obtained via DDC which is a simple protocol over I☬.

In order to determine the graphics modes that are supported on a connected monitor it is necessary to parse the monitor's EDID information.

You need to be able to access PCI configuration space and find MMIO regions that are determined by BARs.

You should know what horizontal/vertical active, total, sync start/end and blanking start/end values mean and what a pixel clock is. Especially the part about display timings it is still relevant for modern graphics cards. It does not yet explain how the GPU can be used to accelerateĢD and 3D graphics operations via shader programs.īefore trying to implement a native driver for your OS, make sure you understand the basics first. In particular it explains how to change the graphics resolutionĪnd how to manage the hardware provided frame buffers. This page explains how to drive a subset of those cards. Wikipedia contains a list of all those chips. Most notably modern Intel processors often come with Intel HD graphics chips. Intel has produced a number of graphics chips that are integrated into their chipsets and processors.

3.3.5 Disabling the legacy VGA emulation.

3.3.4 Enabling and disabling connectors.

3 Generation 4 GMA desktop chips (aka Intel G45).

Intel graphics integrated